The present invention relates to an ATM (Asynchronous Transfer Mode) cell segmentation and reassembly circuit to be provided in a terminal of an ATM transmission network.
In the ATM transmission network, messages from a sender terminal are transmitted being loaded on cells which are addressed to a receiver terminal designated by the sender terminal.
FIG. 4 is a block diagram illustrating a conventional cell segmentation and reassembly circuit provided in an ATM terminal for exchanging packet data by way of an ATM transmission network. The cell segmentation and reassembly circuit of FIG. 4 comprises a received-cell processing unit 500, a tranismission-cell processing unit 600, a CPU (Central Processor Unit) 700 for controlling the received-cell processing unit 500 and the transmission-cell processing unit 600, a received-packet memory 800, and a transmission-packet memory 900.
Received cells, which have been transmitted towards the ATM terminal through the ATM transmission network, are reassembled into packets by the received-cell processing unit 500 and stored in the received-packet memory 800 under control of the CPU 700. Packets to be transmitted from the ATM terminal to another terminal through the ATM transmission network are once stored in the transmission-packet memory 900, read out from the transmission-packet memory 900 and segmented by the transmission-cell processing unit 600 into cells to be transmitted towards the ATM transmission network under control of the CPU 700.
A problem of the conventional cell segmentation and reassembly circuit of FIG. 4 is that it is inconvenient for relaying BUS (Broadcast and Unknown Server) packets of LAN (Local Area Network) emulation, that is, broadcast packets, multi-cast packets or packets whereof ATM addresses are unknown, as will be described in the following paragraphs.
Packets reassembled from received cells are stored (data line 13) in the received-packets memory 800 according to control (control line 16) of the CPU 700. When a packet is to be relayed, the CPU 700 copies the packet stored in the received-packet memory 800 into the transmission-packet memory 900 (data line 14) and notifies (control line 17) the address of the packet copied in the transmission-packet memory 900 to the transmission-cell processing unit 600, whereby the packet is read out (data line 15) from the transmission-packet memory 600 and segmented into transmission cells by the transmission-cell processing unit 600 to be transmitted through the ATM transmission network.
Here, the copy of the relaying packet between the received-packet memory 800 and the transmission packet 900 and notification to the transmission-cell processing unit 600 of the address of the relaying packet stored in the transmission-packet memory 900 are both performed by software processing executed by the CPU 700, needing comparatively long time for relaying the BUS packets in the LAN emulation,
Furthermore, the relaying packet uses memory resources both in the received-packet memory 800 and the transmission-packet memory 900 which should be prepared separately.
This is another problem.
Therefore, a primary object of the present invention is to resolve above problems and provide an ATM-cell segmentation and reassembly circuit wherein the BUS packets can be relayed at high speed without dissipating memory resources.
In order to achieve the object, an ATM-cell segmentation and reassembly circuit of the invention comprises:
a receiving-cell processing unit for reassembling received cells into received packets;
a transmission-cell processing unit for segmenting transmission packets into transmission cells;
a packet memory for storing the received packets and the transmission packets; and
a descriptor section shared by the received-cell processing unit and the transmission-cell processing unit for registering reception descriptors to be used for reassembling the received cells and transmission descriptors to be used for segmenting the transmission packets, wherein a reception descriptor used for reassembling the received cells into a received packet is used as a transmission descriptor for segmenting the received packet into the transmission cells when the received packet is to be relayed towards another terminal.
Each of the reception descriptors and the transmission descriptors has a common format describing information, which includes a stored address in the packet memory, VPI/VCI (Virtual Path Identifier/Virtual Channel Identifier) information and packet length, of respective one of the received packets and the transmission packets.
Data of the received packet to be relayed is read out by the transmission-cell processing unit from an address of the packet memory where the received packet to be relayed is stored by the received-cell processing unit, referring to the stored address described in the reception descriptor used for reassembling the received cells into the received packet to be relayed.
Therefore, no software processing is needed for copying data of the relaying packet from a received packet memory into another transmission packet memory, for example, or re-preparing a transmission descriptor for notifying the address of the relaying packet stored in the transmission packet memory.
Furthermore, there is no need to prepare the reception packet memory and the transmission packet memory separately, enabling efficient usage of memory resources.